Fully checked electronic printing system



June 6, 1967 D. F. SWEENEY 3,323,450

FULLY CHECKED ELECTRONIC PRINTING SYSTEM Filed Sept. 1, 1964 3heets-Sheet 1 FIG. I

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A I vmo 2.52 mwzma v 522$. om. wwcj @231 onom EmEEo INVENTOR DAVID ESWEENEY ATTORNEYS United States Patent 3,323,450 FULLY CHECKEDELECTRONIC PRINTING SYSTEM David F. Sweeney, Wellesley, Mass., assignorto Anelex Corporation, Boston, Mass, a corporation of New HampshireFiled Sept. 1, 1964, Ser. No. 393,678 11 Claims. (Cl. 101-93) Myinvention relates to high speed printers, and more particularly to asystem for checking the operation of a serially operated high speedprinter to detect errors which may occur during aprinting cycle.

Serially operable highspeed printers have been developed in which aselected group of character type faces are serially presented to aprinting location at which they may be impacted by a print hammer toform an impression of the character on a recording sheet. Ordinarily, aset of characters is provided for each column to be printed on therecording sheet, and the characters are arranged in axially spaced fontsalong the surface of a constantly rotating print wheel, the fonts beingskewed circumferentially so that a given character arrived in printingposition successively for the successive columns to be printed. Means isprovided for storing a group of character codes, one for each column ina line to be printed, each identifying the character to be printed inthe associated column. As each skewed row of characters of a given kindapproaches the printing position for the first column, the storage meansis scanned, the character code for a given column being scanned as thecharacter for that column in the row under consideration approaches theprinting position, and all of the stored characters for the line to beprinted which agree with the character in the row coming into positionare printed by actuating their associated print hammers. The storedcharacters being scanned are rewritten in the storage unit aftercomparison with the character then coming into position, and thescanning is repeated as the next skewed row of characters comes intoposition.

In such a system, it is possible that a print hammer will fail to beactuated even though a true comparison has been made between a characterstored for that column and a character coming into printing position. Itis also possible that, even though a stored character may agree with acharacter coming into position, the agreement will not be registered andthe hammer will fail to be actuated. Further, it may occasionally occurthat a hammer is fired which should not have been fired. It is theobject of my invention to facilitate the detection of errors of thiskind, so that information erroneously recorded may be easily detectedand the machine may be stopped for necessary repairs when indicated bythe occurrence of persistent errors.

Briefly, an error checking system for a serially operated printer inaccordance with my invention comprises apparatus for checking that ahammer has been actuated each time agreement is detected between astored character code and a character code corresponding to a charactercoming into printing position, and also checking that no hammer has beenfired unless agreement has been found. The system of my invention alsoincludes apparatus for producing an alarm signal if a print cycle isstarted but not properly completed by the printing of each storedcharacter and the erasing of the character from the storage system. Theapparatus is controlled by signals which are normally provided for printcycle control purposes, or which may be readily made available in a highspeed printing system. In accordance with one embodiment of myinvention, I provide a timer which is started in response to a startprint signal at the beginning of a 3,323,456 Patented June 6, 1967 "iceprinting cycle, and which produces a sampling pulse at the end of aperiod corresponding to a full revolution of the print roll. The startprint signal is also used to set a bistable circuit to a first state.During the printing cycle, characters which have been printed are erasedfrom the memory, and when all characters have been erased from thememory, a signal is produced which indicates that printing has beencompleted. This signal is employed to reset the bistable circuit to anopposite state. Apparatus is provided for producing an alarm signal ifthe bistable circuit has not been reset when the timer produces itssampling pulse, and for resetting the timer when the bistable circuit isreset.

Apparatus is also provided for checking the operation of the printerduring a printing cycle. In a serially operable high speed printer, anagreement pulse is produced each time a stored character is found to bethe same as a character type face coming into printing position.'Theseagreement pulses are employed in the apparatus of my invention to set asuitable bistable circuit, such as a center-tripped flip-flop, to areference state. Means is provided for detecting the operation of eachhammer actuating circuit, to produce a hammer echo pulse each time ahammer is actuated. These hammer echo pulses are used to set thebistable circuit to its opposite state. A suitable sampling pulse isprovided, following each time in which an agreement pulse may beproduced by a time permitting the actuation of a hammer, to sample thestate of the bistable circuit and produce an alarm signal if it is inits reference state. The circuit is so arranged that whether anagreement pulse occurs without a hammer actuating pulse, or a hammeractuating pulse occurs Without an agreement pulse, the bistable circuitwill be set in its reference state when the sampling pulse occurs.

The apparatus of my invention will best be understood by reference tothe following detailed description, together with the accompanyingdrawings, of a prefer-red embodiment thereof.

In the drawings,

FIG. 1 is a schematic elevational view of a portion of a high speedprinter, showing the relation of the print roll and print hammers;

FIG. 2 is a schematic perspective sketch of the portion of the highspeed printer shown in FIG. 1 and also showing the manner in whichcharacter codes may be generated as various characters come intoprinting position;

FIGS. 3a and 3b, when arranged horizontally side by side with FIG. 3a atthe left, comprise a schematic wiring diagram of an error checkingsystem for a high speed printer in accordance with my invention.

Referring first to FIGS. 1 and 2, I have shown a portion of a high speedprinter comprising a series of print hammers such as the hammer 1, eachprovided with an actuating coil such as the coil 2. The hammers aredisposed in a row defining a printing station adjacent the surface of aconstantly rotating print roll 3. A carbon ribbon such as 4 and arecording means such as a sheet of paper 5 may be disposed between thehammers and the print roll in the manner indicated, and fed byconventional apparatus which stops the paper in printing position foreach line to be printed.

As indicated in FIG. 2, a series of fonts of characters, one for eachhammer corresponding to a column to be printed, is axially spaced alongthe surface of the print roll 3 and circumferentially staggered so that,for example, the letter A for the first column arrives in printingposition slightly before the letter A for the second column, and so on.While various other techniques may be employed for serially delaying thearrival of characters for the successive columns in printing position,such as skewing the print roll axis or progressively delaying the hammeractuating circuits, the arrangement shown is preferred.

As indicated schematically in FIG. 2, a shaft encoder 6 is providedwhich may comprise a disc 8 on the shaft 7 of the print roll 3, providedwith a coded row of radial apertures for each character in the fonts ofcolumns around the print roll, each row comprising six spaces eachpierced with an aperture or not according as a corresponding bit in acharacter code defining the associated character is l or 0, a seventhspace, if desired, to define a parity bit, an eighth space pierced withan aperture to indicate the location of the character. If desired, aspecial character comprising a symbol to be printed when an illegitimatecharacter has been found in memory may be located in each font, andmarked by a single aperture on the disc 8 radially displaced from theeightspaced rows just described.

The disc 8 is placed between a bank of nine lamps, not shown, and acorresponding bank of photocells schematically indicated at 9, toprovide pulses comprising a character code group of seven pulses foreach legitimate character to be printed, a single pulse for the specialcharacter, and a character pulse for each character. It will be apparentthat more or fewer character code pulses could be provided if desired,to produce a code having a capacity consistent with the number ofcharacters in each font, but for an alphanumeric font comprisingsixtyfour characters six pulses are conveniently provided to define thecharacters using a full binary count, with a seventh output pulseprovided to introduce a parity bit, by conventional techniques, forpurposes of checking the parity of the stored character codes. As willappear, the parity bit is not essential because the apparatus of myinvention is capable of checking parity, as well as illegitimatecharacters, without a special parity bit.

Referring next to FIGS. 3a and 312, I have shown, in connection with anoperation checking system in accordance with my invention, so much onlyof a serially operable printer system as is necessary to understand thestructure and operation of the apparatus of my invention. In particular,various circuits for timing and programming the storing and processingof information in a high speed printer, well known to those skilled inthe art, have not been shown, and various functions necessarilyperformed in such a system and helpful in understanding the apparatus ofmy invention have been indicated quite schematically.

As shown, the system comprises a timing means 10 consisting of apparatusfor producing control pulses for use in timing the operation of thesystem. While various conventional means may be employed for thispurpose, I have shown an AND gate A1 of conventional constructionenabled when three signals are simultaneously applied to its three inputterminals to produce a signal at its output terminal for setting aconventional flip-flop FFl to a first state. The flip-flop FFl is set toits first state at the end of each print cycle, as will appear. A startprint signal, generated in any known conventional manner to indicatethat such operations as the feeding of paper and the loading of a newline of characters into memory are complete, is employed to set theflip-flop FFI to a second state at the beginning of each print cycle.

When the flip-fiop F1 1 is in its first state, it produces a signal at aselected one of its output terminals labelled clock-stop and serving toreset a conventional gated one-shot multivibrator CS1 by removing agating level from its input terminal G to permit it to respond totrigger pulses applied to its input terminal T. Suitable gated one-shotmultivibrators for use as 081, and other one-shot multivibrators to bedescribed, are shown and described in copending US. application Ser. No.358,853, filed on Apr. 10, 1964, by John C. Sims, Ir., for Variable WordLength Internally Programmed Information Processing System, and assignedto the assignee of my application.

Trigger pulses are at times applied to the one-shot multivibrator 051 bya conventional OR gate 0R1, which produces an output pulse when asuitable input signal is applied to either of its input terminals. Afirst input terminal at times receives a signal from a conventional ANDgate A2, when suitable signals are simultaneously applied to its twoinput terminals. The second input terminal of the gate 0R1 at timesreceives a signal, labelled recycle from the output terminal of aconventional one-shot multivibrator CS2, in response to a triggeringpulse from the output terminal of the multi vibrator 081. In practice,the time delays of the multivibrators OS1 and 082 might be, for example,2 microseconds and 8 microseconds, respectively. As shown, twoadditional conventional one-shot multivibrators CS3 and 054 areconnected in series, with the input trigger terminal of themultivibrator 053 connected to the output terminal of the multivibrator081. Each of the multivibrators OS3 and 084 may have delays of 2microseconds if the other time delays are as given above.

The operation of the timing means 10 will be apparent to those skilledin the art. Briefly, at the start of a print cycle the clock stop levelwill be removed by operation of the flip-flop FFl. A level in printcycle, produced as described below, will be applied to one inputterminal of the AND gate A1. The first character pulse produced by theshaft encoder (FIG. 2) will cause the gate A2 to produce an outputsignal, applied through the gate 0R1 to trigger the multivibrator 051.Two microseconds later, assuming the values given above, an output pulsewill be produced by the multivibrator 0S1, serving to trigger themultivibrators OS2 and CS3 and acting as the first of a series of readsample pulses. After a further delay of two microseconds, a pulse willbe produced by the multivibrator 083, used as a write sample signal toallow the entry of a character into memory, as will appear, and also tostep a conventional lO bit shift register SR1 serving to select one often memory address lines in a memory address matrix, to be described.Two microseconds later, the multivibrator 0S4 produces a delayed clockpulse, for purposes to be described. Finally, a new cycle is initiatedby a recycle pulse produced by the multivibrator 0S2 eight microsecondsafter the initial triggering pulse from the multivibrator 051. Thetiming means 10 will continue to cycle in this manner until the clockstop signal is produced by the flip-flop FFI, in a manner to bedescribed.

A core plane memory matrix 14 is provided which may be of a conventionaltype employing 840 ferrite cores arranged in a 7 x array, wired as shownfor the four typical cores 16. Each core is provided with a verticalread line, which is adapted to be energized by a current ofpredetermined value to produce an output pulse on an output sense lineif the core is saturated in one sense, and to produce no output pulse ifthe core is saturated in the opposite sense. Each core is also providedwith a vertical write line and a horizontal input line, each adapted tobe energized with half of the current necessary to saturate the core inthe opposite sense from the sense to which it is driven by the readline, to set the core when half current is applied to both the writeline and the input line for the particular core. Seven input lines areprovided to the horizontal input windings of the core matrix, to whichpulses representing characters identified by a code sequence of six bitsfollowed by a parity bit may be applied.

Reading from and writing into the memory matrix 14 is controlled by amemory address matrix comprising the shift register SR1 described aboveand a second twelve bit shift register SR2, of conventionalconstruction. The shift register SR1 has ten sequential states in eachof which it enables one of ten output lines L1 through L19 to produce anoutput signal enabling one pair of a set of conventional AND gateslabelled AR or AW, plus an address bit identifying numerical sufiix,such as the pair of gates AW1 and ARI. The enabled gate labelled AR-produces an output pulse at the read sample time, and the enabled gatelabelled AW- produces an output pulse at the write sample time.

The output terminals of the AND gates AW- are each connected to theoutput terminals of a different one of ten write amplifiers such as WA1,WAZ, etc. Similarly, the AND gates AR are connected to control readamplifiers such as RAl, RA2, etc. These amplifiers may be of any knownconventional construction. When actuated by a signal from the associatedAND gate, the amplifiers such as WAl and RAl produce a current pulse onvertical write and read lines, respectively, in the memory matrix 14.The shift register SR2 selects the high ordered digit of the memoryaddress from one of twelve groups of ten addresses and the shiftregister SR1 selects one of ten addresses within the group selected bythe shift register SR2. To this end, the shift register SR2 has twelvesequential states in each of which a different line H1 through H12 isenabled in a conventional manner to control an associated gate WRAlthrough WRA12 to serve as a current sink. The gates such as WRAl may beof any conventional construction, but for example may be NOR gates ofthe type disclosed in the above cited copending application of John C.Sims, ]r., which have output terminals serving as ground level currentsinks when a negative potential is applied to their input terminals.

Each of the gates WRAI through WRA12 is connected to a different set often vertical read lines and ten vertical write lines, isolated by diodesas shown. Within each group associated with a gate such as WRAl, eachread line is connected to a different one of the ten read amplifiers RAlthrough RA10, and each write line is connected to a different one of theten write amplifiers WA} through WA10, in the manner sufiicientlyindicated in the drawing. Thus, in any given state of the shiftregister, at the read sample time full switching current is supplied byone of the read amplifiers such as RA1 and flows to the current sinkprovided by one of the gates such as WRAl, so that one column of thememory is read out in each state of the shift registers.

As indicated in the drawing, when the shift register SR1 is reset fromits tenth state to its first state, a signal step high order is producedin a conventional manner and steps the shift register SR2 to its nextstate. As stepping proceeds, in response to successive write samplepulses, the memory will be scanned from column 1 through column 120. Thewrite sample pulse following the processing of column 120 will produce afinal step high order signal from the shift register SR1, restoring theshift register SR2 to its initial state. At the same time, with the leadH12 energized, the gate A1 in the timing means will produce an outputsignal to set the flipfiop FFl to produce its clock stop level, stoppingthe timing cycle. A new cycle will be commenced by the next characterpulse, as described above.

The horizontal output lines of the core memory matrix 14 are applied inparallel through conventional sense amplifiers SA to a conventionalseven bit register R1, which may comprise a series of flip-flops or thelike. The output of the register R1 is applied in parallel to a clearmemory detector 17, a code comparator 18, and a set of seven re-writegates 19. The construction and function of these units will next bedescribed.

The clear memory detector 17 may comprise a conventional OR gate 0R2 towhich are applied in parallel all of the output signals from theregister R1. Assuming a code in which the presence of a signal capableof actuating the gate 0R2 indicates a 1 bit in the character in theregister R1, the gate 0R2 will produce an output pulse each time anycharacter is stored in the register R1.

The output of the gate 0R2 is connected to one input terminal of abistable circuit here shown as a flip-flop FF2. This flip-flop may be ofconventional construction, adapted to be set to a reference state by theoutput of the gate 0R2, and reset to an opposite state by an outputpulse produced by a conventional AND gate A3. The AND gate A3 has twoinput terminals, to one of which the character pulses from the characterpulse generator 8 in FIG. 2 are applied, and to another of which an inprint cycle signal, to be described, is applied.

One output terminal of the flip-flop FFZ is connected to one inputterminal of a conventional AND gate A4. A second input terminal of theAND gate A4 is connected to receive the clock stop signal, describedabove. If the flip-flop FFZ is in its reset state on count 121 of thecounter, the AND gate A4 will produce a print-complete pulse to indicatethat the memory has been cleared and all characters stored in it havebeen printed.

The shaft encoder 9 has itsoutput terminals connected to the inputterminals of a conventional eight bit register R2, which may comprise aset of flip-flops or the like. The output terminals of the register R1and the seven terminals of the register R2 representing data and parityare connected to the input terminals of a conventional code comparator18, wherein apparatus of a conventional type well known in the art isprovided for detecting agreement between the output of the shaft encoder9 and the output of the core plane memory matrix 14. The eighth bit ofthe register R2, if provided, stores a bit indicating the approach of anillegitimate character symbol to printing position, for purposes to bedescribed.

The code comparator 18 produces an agreement pulse when agreement isfound between the characters stored in the registers R1 and R2. Thisagreement is applied, through an OR gate 0R4, to the input terminals ofa conventional inverter 24, which, in the absence of an agreement pulse,produces an output signal indicating no agreement that is applied toeach of the seven re-write gates 19. As will appear, a second input tothe gate 0R4 provides a substitute agreement signal under certaincircumstances. As indicated by the typical gates shown, these gates 19may comprise an AND gate such as 25, having one terminal connected tothe no agreement line and a second input terminal connected to one ofthe seven output lines of the register R1. The output terminal of eachof the AND gates such as 25 is connected to the corresponding inputterminal of the core plane memory matrix 14. The storage provided by theregister R1 permits a character stored in the register at the readsample time, and not printed, to be rewritten in the same location inmemory at the write sample time. Characters that have been printed arenot rewritten in memory. However, where 000000 is a legitimate charactercode and parity is not checked, it may be desirable to restore locationsin memory that have been printed to some selected code other than000000, with consequent changes in the logic of the memory cleardetector to ignore the selected code.

Referring to FIGS. 3a and 3b, the flip-flop FF3 is set to one state bythe start print signal derived from the memory clear detector 17. Thestart print signal is also applied to start a timer 31, which may be ofany suitable construction designed to produce an output pulse for eachrevolution of the print roll following the start print signal if notfirst reset by a print complete signal. Any of various known gatedmonostable circuits could be employed for this purpose, but as hereshown, the timer comprises a conventional single shot multivibrator 0S5followed by a conventional AND gate A5 enabled by an in print cyclelevel produced by the flip-flop FF3 when set by the start print signaland removed when the flip-flop FF? is reset by a print complete signal.Typically, the duration of the output pulse of the one-shotmultivibrator OSS would be about 760 milliseconds in high speed printingsystems operating at a drum speed of 1000 rpm.

The output pulse of the timer 31 is supplied to one input terminal of aconventional flip-flop FF4, the other input terminal of which isconnected to any suitable resetting circuit, such as a current sourcecontrolled by a manual switch, to produce an alarm reset signal whendesired. A selected output terminal of the flip-flop FF4 produces analarm level labelled alarm 2 to energize any desired indicating orcontrol equipment, here typified as an indicator lamp K2. Theillumination of this lamp K2 indicates that a print cycle has beenstarted and followed by a complete revolution of the print roll withoutthe production of a print complete signal, indicating an error inoperation.

The agreement pulse produced by the code comparator 18 is supplied to adistributor 38, which may be timed by the read sample signals tosequentially distribute agreement pulses to the appropriate one of 120hammer driver circuits during a scanning cycle. As indicated, thedistributor may comprise 120 gates such as the AND gate 39, each havingone terminal connected to the agreement pulse line, another terminalconnected to one of the ten low order address lines such as L1, andanother input terminal connected to one of the twelve high order addresslines such as H1. The hammer driver circuits may be of any conventionaltype known to those skilled in the -art,and are here shown as comprisinga power amplifier 41 energized by the output of the corresponding ANDgate 39 in the distributor 38. The output terminals of the amplifier 41are connected through the coil 2 of the associated hammer, and are alsoconnected through a coupling capacitor such as 42 to one of 120 hammerecho pulse lines. The hammer echo pulse lines are connected to an ORgate R3, of conventional construction, which also has an input terminalconnected to the agreement pulse line. The gate 0R3 accordingly producesan output pulse each time a hammer is fired, and also each time anagreement pulse is produced. This output pulse is applied to acenter-tripped terminal of a conventional center-tripped fiip-flop F FE,to change its state each time the OR gate 43 produces an output pulse.As shown, the fiipdlop FFS is also provided with a direct set terminalcontrolled by the start print signal to assure that the flip-flop willbe in a reference state at the beginning of each print cycle. One outputterminal of the fiip-flop FPS is connected to one input terminal of aconventional AND gate A6, which has a second input terminal connected toreceive delayed clock pulses produced as described above. Thus, aftereach agreement pulse, followed by the firing of a corresponding hammer,the flip-flop FPS changes state twice and if it does so the arrival ofthe next delayed clock pulse will not cause the AND gate A6 to producean output pulse. However, if one or the other of the setting pulses forthe flip-flop FPS is missing, the delayed clock pulse will cause anoutput pulse to be produced by the AND gate A6 to set a conventionalflip-flop P1 6 to produce an alarm 1 level, here shown as energizing anindicator lamp K1. The illumination of this lamp will indicate eitherthat a hammer has been fired which should not have been fired or that ahammer has not been fired which should have been fired.

Having described the structure of one embodiment of my invention, itsoperation will next be described. Referring first to FIG. 3a, the memoryis first loaded with 120 character signals in any conventional manner,not shown. After the memory has been loaded, a start print pulse may beproduced in a conventional manner and the flip-flop F1 3 will be set toproduce an in print cycle level to enable the AND gate A2 to start thetiming means at the next character pulse. When the first character pulseappears following the setting of the flip-flop F1 3, it will provide apulse to the gate CR1 and then trigger the multivibrator 083 to begin ascanning cycle. At the same time, the gate A3 will reset the flip-flopFFZ. As the first vertical read line is energized in the core planememory matrix 14, the character stored for the first column is read intothe register R1 and applied to the code comparator 18. Assuming that itis in agreement with the code produced by the shaft encoder 9,

an agreement pulse is applied to cut off the rewrite gates 19 andprevent the stored character from being rewritten in the memory, andalso to actuate the first gate 39 in the distributor 3:8 to apply ahammer driving signal to actuate the amplifier 41 for the first columnhammer in the hammer driver circuits 40. The firing of this hammersupplies an output pulse to the OR gate 0R3. As described above, theflip-flop FPS is first set by the agreement pulse, and then reset by ahammer echo pulse by the gate 0R3. Accordingly, when the delayed clockpulse following the read sample pulse which energized the first columnread line occurs, the gate A6 will be disabled and the alarm flip-flopFF6 will not be set.

At the same time that the first character for the first column was readout to the code comparator 18, one or more pulses were applied inparallel to the OR gate 0R2 in the memory clear detector 17 to set theflip-flop FFZ. The scanning cycle will then continue, with each storedcharacter in the memory matrix 14 being sequentially compared with thefirst character supplied by the shaft encoder 9, and whether or not anyfurther outputs are produced by the OR gate 0R2, the memory cleardetector will not respond during this cycle because the flip-flop FFZhas been set. However, any disagreement between an agreement pulse and ahammer echo pulse will cause the flip-flop FPS to be set to the state inwhich the gate A6 will be enabled to pass the next delayed clock pulse.If this occurs, the flip-flop F1 6 will be set to its alarm state andthe indicator lamp K1 will be illumined. When count 121 is reached inthe first scanning cycle, that is, when lead H12 is energized and thestep high order signal is produced, the gate A1 in the timing means 10will reset the flip-flop FFl to its clock stop state, and no furtheroperation will take place until the next character pulse is received.

As each successive character is presented by the shaft encoder 9 to thecode comparator 18, the scanning cycle just described will be repeated,with characters producing an agreement with the output of the shaftencoder being printed, and erased from the core plane memory matrix 14.When the last stored character has been printed, a final scanning cyclewill take place, in response to the character pulse following thecharacter pulse for the last character in the font. This character pulsewill cause the timing means It) to be started as before, and begin itscounting cycle. The flip-flop FFZ will also be set by the characterpulse, and all the columns of the memory matrix 14 will be successivelyscanned on the counts of the counter from one to 120. Since all of thecharacters have been erased from memory, the OR gate 0R2 will produce nooutput pulse during this scanning cycle, and the flip-flop FFZ willremain set. Accordingly, when the clock stop level is produced, theflip-flop FFZ will enable the gate A4 to pass a print complete pulse.This print complete pulse will be applied to reset the flip-flop FFZwhich was set by the start print signal. At the same time the startprint signal was applied, the timer 31 was started by triggering thesingle shot multivibrator 085. When a complete revolution of the printroll has been made, the timer 31 will produce its output pulse to enablethe AND gate A5. However, since the flip-flop F1 3 has been reset by theprint complete signal, no output pulse will be produced. On the otherhand, if the print complete level had not been produced, the gate A5would set the flip-flop P1 4 to provide the alarm 2 level to energizethe indicator lamp K2.

Various controls may be exercised in response to the alarm 2 signalprovided by the flip-flop FF4. If desired, the printer may be stopped,or printing may be continued by ignoring the alarm indication ormanually overriding it if the flip-flop FF! is normally connected tostop the printer. Alternatively, it may be desirable to locate anillegitimate character symbol in the font for each character on theprint roll, and to follow the memory scan in which the flip-flop F1 4was set by a scan in which the 9 illegitimate character symbol isprinted in each column for which the gate R2 produces an output pulse.For this purpose, the outputs of the gate CR2 and the flip-flop FF4 inits alarm 2 state may be applied to an AND gate A7, the output of theAND gate A7 being combined in an OR gate 0R4 with the output of thecomparator 18 to provide the agreement signal for the system. Thelocation of the illegitimate character symbol on the print roll isimmaterial, because printing may begin on any character pulse. However,to carry out the illegitimate character printing operation at the propertime, either a character code identifying the illegitimate charactermust be provided on the code wheel 8 in FIG. 2, to be detected by adecoding network controlled by the comparator 18, or preferably, aseparate illegitimate character bit is produced by the shaft encoder 9'as described above, stored in the register R2 as the eighth bit, andapplied as the third input to the gate A7, as shown.

It will be apparent that, while I have shown various logical functionsimplemented by AND, OR, and NOR gates, other implementing circuits couldbe substituted by applying appropriate known logical transformations.

While I have described my invention with reference to the details of aspecific embodiment, many changes and variations will occur to thoseskilled in the art upon reading my description, and such can obviouslybe made without departing from the scope of any invention.

Having thus described my invention, what I claim is:

1. Apparatus for checking the operation of a serially operable highspeed printer of the type comprising a plurality of print hammers, acharacter code generator for serially producing codes representingcharacters on a print roll successively arriving in printing positionadjacent said hammers, storage means for storing a code representing acharacter to be printed for each hammer, code comparing meanssynchronized with a train of clock pulses for scanning said storagemeans once for each character code produced by said code generator andproducing an agreement signal for each corresponding stored code, andmeans controlled by each agreement signal for actuating thecorresponding hammer, said apparatus comprising, bistable circuit meansalternately actuated to opposite states by a succession of appliedsignals, means for applying the agreement signals to said bistablecircuit means, means responsive to the actuation of any of the hammersfor applying a signal to said bistable circuit means, and means forsampling the state of the bistable circuit means, at a time after eachclock pulse sufiicient to permit the actuation of a hammer, forproducing an alarm signal if an odd number of signals have been appliedto said bistable circuit means.

2. In a serially operable high speed printer, a plurality of printingtransducers, one for each column in a line to be printed, recyclingmemory means for storing a series of character codes, one for eachprinting transducer, and responsive to a sequence of applied scanningsignals for producing output code corresponding to the stored codes andrewriting them in the memory, encoding means for producing a series ofcharacter codes representing a series of characters available forprinting by said transducer, means for producing a series of scanningsignals for each code produced by said encoder means, code comparatormeans for producing an agreement signal in response to two applied codeshaving a predetermined relationship, means for applying the codesproduced by said encoder means to said comparator means, meanscontrolled by said scanning signals for sequentially applying thecharacter codes stored in said recycling memory means to said comparatormeans, a gate means for each printing transducer operable when enabledfor operating the transducer in response to an agreement signal fromsaid comparator, means controlled by said scanning signals forsequentially enabling said g-ate means as each stored code correspondingto a transducer is applied to said comparator means to permit thecorresponding transducer to be actuated if an agreement signal isproduced, pulse generating means responsive to said transducers forproducing an output signal for each transducer that is actuated, meansfor registering the parity of the sum of the agreement signals and thesignals produced by said pulse generating means, means controlled bysaid scanning signals for producing a series of delayed signals, one foreach scanning signal and occurring before the next scanning signal, andmeans controlled by said delayed scanning signals and said registeringmeans for producing an alarm signal if the registered parity is odd.

3. In a high speed printing system, a plurality of printing transducers,one for each column in a line to be printed, means for producing a trainof clock pulses, means synchronized with the clock pulse train forapplying actuating signals to said transducers, means controlled by saidtransducers for producing an output signal in response to the actuationof a transducer, means controlled by said output signals and saidactuating signals for registering the parity of the sum of said signals,means controlled by said clock pulse train for producing a delayed clockpulse for each clock pulse in said train, and means controlled by saiddelayed clock pulses and said registering means for producing an alarmsignal when the registered parity is odd.

4. In a high speed printing system, a series of printing transducersarranged in a row defining a print station adjacent a rotating printroll bearing a font of characters for each transducer, storage means forstoring a series of character codes, one for each transducer, shaftencoder means synchronized with the print roll for producing a series ofcharacter codes representing characters approaching the print station,means synchronized with the print roll for producing a series ofcharacter pulses, one for each code produced by said shaft encodermeans, means controlled by said character pulses for producing a seriesof scanning signals, scanning means controlled by said scanning signalsand operatively connected to said storage means for sequentiallyproducing character codes coresponding to the codes stored for eachtransducer, code comparator means controlled by said shaft encoder meansand said scanning means for producing an agreement signal for eachstored code corresponding to the code produced by the shaft encodermeans, a gate means for each transducer operable when enabled to actuatethe transducer in response to an agreement signal produced by saidcomparator, means controlled by said scanning signals for sequentiallyenabling said gate means as corresponding stored characters are scanned,gate means controlled by said transducers for producing a signal eachtime a transducer is actuated, registering means controlled by saidagreement signals and the signals produced by said gate meansfor'rcgistering the parity of their sum, delay means controlled by saidscanning signals for producing a delayed signal for each scanningsignal, and means controlled by said registering means and said delayedsignals for producing an alarm signal when the registered parity is odd.

5. In a high speed printing system of the type comprising storage meansfor storing a code representing a character to be printed for eachcolumn in a line to be printed, a constantly rotating print roll bearinga font of characters for each column to be printed, a printingtransducer adjacent each font and operable when energized to print thecharacter then adjacent, a character code generator for producing acharacter code signal identifying each character coming into printingposition, means for scanning said storage means once for each charactercode signal, and means controlled by said scanning means for comparingthe character code signal with the stored character codes and producinga signal for energizing each transducer associated with a stored codewhich agrees with the character code signal, code checking apparatuscomprising registering means controlled by said comparing means and saidtransducer means for l. l registering the parity of the sum of saidenergizing signals and the number of transducers energized by saidsignals, and delayed gate means controlled by said registering means andsaid scanning means for producing an alarm signal when the registeredparity is odd.

6. In apparatus for checking the operation of a serially operated highspeed printer of the type comprising a constantly rotating print rollbearing a plurality of fonts of characters sequentially presented to aprint station defined by a row of print hammers, one for each font, thecombination comprising storage means for storing a character coderepresenting a character to be printed for each of said hammers, meansfor producing a start print signal, code comparing means enabled by saidstart print signal and actuated as each character on said fontsapproaches the print station for sequentially removing the charactercodes from said storage means and comparing them with a comparison coderepresenting the character coming into position, means controlled bysaid comparing means when a stored code agrees with the comparison codefor actuating the hammer associated with the stored code, meanscontrolled by said comparing means when a stored code does not agreewith the comparison code for replacing the stored code in the storagemeans, a bistable circuit having first and second states, meanscontrolled by said start print signal for setting said bistable circuitto its first state, means controlled by said storage means for producinga print complete signal when no codes remain in said storage means,means controlled by said print complete signal for setting said bistablecircuit to its second state, and timing means controlled by said startprint signal and said bistable circuit in its first state for producingan alarm signal at a time following the start print signal adequate topermit a line to be printed.

7. The apparatus of claim 6, in which each font of characters includes aselected character representing any illegitimate character, and furthercomprising means synchronized with said print roll for producing anillegitimate character signal when said selected characters approach theprint station, a second bistable circuit, means controlled by said alarmsignal for setting said second bistable circuit to a predeterminedstate, and means controlled by said sccond bistable circuit in saidpredetermined state, said storage means, and said illegitimate charactersignal for actuating each hammer for which any code is stored to printthe selected character in the corresponding column.

8. In a high speed printer, a core plane memory matrix for storing aplurality of character codes, one for each column in a line to beprinted, an array of printing means each sequentially operable to printone of a predetermined series of characters, code generating meanssynchronized with said printing means for producing a series of codesrepresenting the different characters which may be printed as theprinting means becomes operable to print them, means for producing astart signal, sequential comparator means enabled by said start signaland synchronized with the code generating means for sequentially readingthe stored codes of the memory matrix and comparing them with the codeproduced by the code generating means, means for restoring to the memorymatrix the codes read out of the matrix which do not agree with the codeproduced by the code generating means, means for detecting the presenceof codes in said matrix and producing a print complete signal when nocodes remain in the matrix, a bistable circuit, means controlled by saidstart print signal for setting said bistable circuit to a first state,means controlled by said print complete signal for setting said bistablecircuit to a second state, and timing means controlled by said startprint signal and said bistable circuit in its first state for producingan alarm signal after said code generating means has produced codesrepresenting all characters 12 which may be printed if the printcomplete signal does not first set said bistable circuit to said secondstate.

9. Apparatus for checking the operation of a high speed printer of thetype comprising means synchronized With a train of character pulses forcomparing character codes stored for each column to be printed withcharacter codes representing characters in printing position andproducing signals for firing hammers associated with each column inwhich the stored code agrees with the code for the character in printingposition, comprising a bistable circuit, means controlled by the signalsproduced by said comparing means for setting said bistable circuit to afirst state, means controlled by the firing of any hammer for settingthe bistable circuit to a second state, means for producing a series ofdelayed clock pulses lagging the system synchronizing train by an amountsuificient to permit the firing of a hammer, and gate means controlledby said delayed clock pulses and said bistable circuit in its firststate for producing an alarm signal.

10. Apparatus for checking the operation of a high speed printer of thetype comprising a plurality of hammers, sequentially operable means foractuating the hammers as characters coming into printing position matchcharacter codes stored for the hammers, means for producing a startprint signal, and means for producing a print complete signal, saidapparatus comprising a bistable circuit, means controlled by said startprint signal for setting said bistable circuit to a first state, meanscontrolled by said print complete signal for setting said bistablecircuit to a second state, and timing means controlled by said startprint signal and said bistable circuit in its first state for producingan alarm signal delayed from the start print signal by an amountsufficient to permit all of said hammers to be actuated if said printcomplete signal is not first received.

11. A fully checked serially operable high speed printing systemcomprising an array of printing transducers, cyclically operable meansfor placing a series of characters successively in printing positionrelative to said transducers, means for producing a start print signal,memory means for storing a series of character codes, one for eachtransducer, scanning means enabled by said start print signal forsequentially reading out of the memory means all of the stored codesonce for each character coming into position, code comparing means forcomparing the codes read out with each character coming into printingposition and producing an agreement signal for each agreement between acode read out of the memory means and the character coming intoposition, means controlled by said code comparing means for reading backinto the memory means each code not in agreement with the charactercoming into position, means controlled by said scanning means and saidagreement signals for actuating the transducer associated with a coderead out of the memory means when an agreement signal is produced, meanscontrolled by said transducers for producing an output signal for eachtransducer that is actuated, registering means controlled by saidagreement signals and said output signals for registering the parity oftheir sum, means controlled by said scanning means for producing aseries of delayed signals, one for each character code read out of thememory means, gate means controlled by said delayed signals and saidreigstering means for producing a first alarm signal if the registeredparity is odd, a bistable circuit, means controlled by said start printsignals for setting said bistable circuit to a first state, meanscontrolled by said memory means for producing a print complete signalwhen said memory means is cleared of stored characters, and timing meanscontrolled by said start print signal and said bistable circuit in itsfirst state for producing a second alarm signal delayed by an amount atReferences Cited UNITED STATES PATENTS 2,941,188 6/1960 Flechimer et a1.340-174 3,064,561 11/1962 Mauduit 101-93 3,066,601 12/1962 Eden 101-931% Deerfield 101-93 X Sweeney 101-93 Marsh 340-1725 Barbagallo et a1.101-93 X W00 101-93 X W'ILLIAM B. PENN, Primary Examiner.

P. R. WOODS, Assistant Examiner.

1. APPARATUS FOR CHECKING THE OPERATION OF A SERIALLY OPERABLE HIGHSPEED PRINTER OF THE TYPE COMPRISING A PLURALITY OF PRINT HAMMERS, ACHARACTER CODE GENERATOR FOR SERIALLY PRODUCING CODES REPRESENTINGCHARACTERS ON A PRINT ROLL SUCCESSIVELY ARRIVING IN PRINTING POSITIONADJACENT SAID HAMMERS, STORAGE MEANS FOR STORING A CODE REPRESENTING ACHARACTER TO BE PRINTED FOR EACH HAMMER, CODE COMPRARING MEANSSYNCHRONIZED WITH A TRAIN OF CLOCK PULSES FOR SCANNING SAID STORAGEMEANS ONCE FOR EACH CHARACTER CODE PRODUCED BY SAID CODE GENERATOR ANDPRODUCING AN AGREEMENT SIGNAL FOR EACH CORRESPONDING STORED CODE, ANDMEANS CONTROLLED BY EACH AGREEMENT SIGNAL FOR ACTUATING THECORRESPONDING HAMMER, SAID APPARATUS COMPRISING, BISTABLE CIRCUIT MEANSALTERNATELY ACTUATED TO OPPOSITE STATES BY A SUCCESSION OF APPLIEDSIGNALS, MEANS FOR APPLYING THE AGREEMENT SIGNALS TO SAID BISTABLECIRCUIT MEANS, MEANS RESPONSIVE TO THE ACTUATION OF ANY OF THE HAMMERSFOR APPLYING A SIGNAL TO SAID BISTABLE CIRCUIT MEANS, AND MEANS FORSAMPLING THE STATE OF THE BISTABLE CIRCUIT MEANS, AT A TIME AFTER EACHCLOCK PULSE SUFFICIENT TO PERMIT THE ACTUATION OF A HAMMER, FORPRODUCING AN ALARM SIGNAL IF AN ODD NUMBER OF SIGNALS HAVE BEEN APPLIEDTO SAID BISTABLE CIRCUIT MEANS.